| 释义 |
emitter-coupled logic circuits(ECL)
发射极耦合逻辑电路;［射极耦合逻辑电路］
A logic circuit in which the circuit generates its own clock pulse independently of the clock pulse for logically preceding or following circuits. This allows d ifferent circuits to work at their own speeds and not be dependent on a clock pulse which must run at the speed of the slowest circuit.
产生自身时钟脉冲的一种逻辑电路,这种脉冲与前级或后级逻辑电路的时钟脉冲是无关的,因而允许不同的电路以其自身的速度操作,而与必须按最慢电路速度运行的时 钟无关。 |