| 释义 |
state table 状态表 A list of the outputs of a logic circuit based on the inputs and previous outputs. The logic circuit includes some memory devices and cannot be described by a simple truth table. 根据其输入和先前的输出决定的逻辑电路输出的一种表。该逻辑电路包含有一些记忆元件,并且不能用简单的真值表来描述。 |